1. Field of the Invention
The present invention relates generally to semiconductor packages, and more specifically to power management of semiconductor packages.
2. Background Art
Today, system-on-chip (SOC) process geometries are shrinking further into deep sub-micron regions to provide greater logic capacity for higher performance. However, these high-performance SOCs also bring corresponding demands for power consumption. In order to adequately meet these power demands, increasingly costly package designs and cooling configurations have been developed.
Efficient SOC designs in a compact form factor is highly desirable, particularly for heavily loaded data center applications where many SOCs may run in parallel, or in mobile battery-powered applications where power consumption and physical footprint must be carefully optimized. Reduction of fabrication costs and increases in yield through simplified package design may also comprise important considerations.
In particular, it is desirable to be able to turn off unused logic blocks, such as processor cores, to reduce power consumption and thermal dissipation demands. Conventionally, this has been done by using on-chip power transistors to switch power, or on-chip regulators for both switching and voltage adjustments. However, efficiency demands often require a large portion of the die to be dedicated to power devices, and power leakage remains an issue even in off-states. Thus, the addition of these power elements to a package lowers efficiency and increases cost, complexity, and form factor.
Accordingly, there is a need in the art for a package configuration that can effectively address the aforementioned difficulty of supplying power for high performance SOCs in a simple, efficient, cost effective, and space saving manner.